Generally, a circuit for reproducing digital data from an optical disc binarizes a signal from the disc by means of a comparator, and then generates a bit synchronous clock by means of a phase-locked loop circuit (hereinafter, referred to as PLL). In order to reduce a phase shift between the data signal and the bit synchronous clock, which is here called jitter, this reproduction circuit has a circuit for adjusting a slice level of the comparator and a phase of the PLL in an earlier time by a jitter detection means or the like. However, these adjustments for the slice level of the comparator and the phase of the PLL cannot be performed independently, without being affected with each other.
FIG. 5 is a diagram showing an example of a data reproduction apparatus having such construction. The conventional data reproduction apparatus shown in figure 5 includes a comparator 31, a PLL 35 that receives an output (data) from the comparator 31, and a phase shift detection means 34. The comparator 31 is provided with a slice level adjustment circuit 32. The PLL 35 includes a phase comparator 1, a phase adjustment circuit 5, a charge pump 2, and a voltage controlled oscillator (hereinafter, referred to also as a VCO) 3.
Hereinafter, an operation of the data reproduction apparatus will be described.
The comparator 31 receives a signal RF from a recording medium such as an optical disc, and binarizes the signal RF to output a binarized signal to the PLL 35 in the latter stage. Here, the slice level that is to be a threshold for the comparator 31 is adjusted by the slice level adjustment circuit 32 so as to minimize the amount of jitter (the phase shift between the data signal and the bit synchronous clock), in view of the amount of phase difference between the comparator output (data) and a phase-locked clock CLK.
The PLL 35 generates a clock CLK from the binarized signal (data) that is outputted from the comparator 31, and outputs the generated clock CLK. Here, the phases of the phase-locked clock CLK that is outputted from the VCO 3 and the data from the comparator 31 are compared with each other, and a control voltage for the VCO 3 is decided by means of the charge pump 2, and fed back to lock the phase.
The phase adjustment circuit 5 controls the amount of current in the charge pump 2 to prevent a phase difference from occurring when an inclination of a rising edge and an inclination of a falling edge of a PLL-generated clock become different from each other due to the difference in the amount of current between a PMOS transistor and a NMOS transistor constituting the charge pump 2. The amount of current is adjusted, for example, by measuring the amount of jitter to minimize the same.
FIG. 6 is a timing chart of the conventional data reproduction apparatus having the above-mentioned structure.
In order to increase the frequency of the phase comparison and improve the accuracy in the phase locking, the phase comparator 1 that constitutes the PLL 35 detects both of rising and falling edges of the data, and compares the respective edges with one edge (rising or falling edge) of the clock CLK. In the aforementioned structure in which the PLL 35 always performs the phase adjustment with the output from the comparator 31 whose slice level has been adjusted, the timing of the falling of the data changes according to duty variations resulting from the slice level adjustment for the data that is outputted from the comparator 31 as shown in FIG. 6, and accordingly the PLL is unfavorably locked so that the phase of a rising edge is also shifted. Thus, it is required to adjust the phase of the data every time when the slice level is adjusted. That is, the phase adjustment for the data cannot be performed before the adjustment of the slice level.
Further, in a state where neither the duty nor the phase is adjusted, it cannot be decided whether the phase shift between the data and the CLK is caused by the phase of the data or the duty. Therefore, it is impossible to perform only the duty correction according to the slice level adjustment, before performing the phase adjustment.
To be more specific, in cases of employing the phase comparator that performs the detection of both edges, it is impossible to perform one of the slice level adjustment and the phase adjustment independently in advance. Therefore, according to the prior art, the optimum slice level and phase must be decided on the basis of all combinations as to the two adjustment patterns.
When there are X possible increments in the slice level adjustment and Y possible increments in the phase adjustment, there are X*Y possible adjustment patterns in the entire data reproduction apparatus. For example when X and Y are 8 bits, i.e., there are 256 increments, respectively, there are 65,536 increments on the whole, and thus the processing time required for the adjustment becomes quite long. The initial adjustment including the jitter correcting control in this data reproduction apparatus is performed at each start of a disc, while it comes to be more difficult to increase the efficiency in the whole apparatus including other functional blocks, as the rotation speed of the optical disc is particularly increased.
Since the conventional phase-locked loop circuit and the control method for the data reproduction apparatus are constructed as described above, and the locking operation in the PLL varies depending on different slice levels of the comparator, the adjustment of the slice level and the phase of the PLL cannot be performed independently without being affected with each other, whereby the time required for the initial adjustment in the data reproduction apparatus cannot be reduced.